Nonvolatile flash memory devices (e.g. 2D NAND Flash or 3D NAND) store information in the form of charge in a flash memory cell. A flash memory cell has a transistor with an additional floating metal gate between the substrate and the transistors gate or a trapping area or any other mechanism to allow charge storage. The charge is stored in the transistor and is injected during an operation known as programming. The charge may be removed during an operation known as an erase operation.
As the charge in the transistor may vary contiguously, it is possible to store more than just one bit per flash transistor by using several charge levels to symbolize different sequences of bits.
FIG. 1 illustrates a prior art voltage level distribution 100 for a 3pbc (bits per cell) flash memory cell. The voltage level distribution includes eight lobes 101-108. Each lobe represents a 3-bit value.
The voltage level distributions of FIG. 1 illustrates non-overlapping lobes, however this is only schematic, and in practical cases the lobes may overlap. For NAND Flash devices, a stressed page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles or read disturb cycles the stress may introduce different noise sources. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These effects are also known as retention.
The 3 bit-per-cell (bpc) cell includes a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of flash memory module may store three logical pages. This physical page is programmed one logical page after the other. The programming includes various types of programming such as MSB programming, CSB programming and LSB programming. Alternatively, all 3 pages in a row may be programmed at once in either a single stage or in several stages. For example, 3 stages may be used for programming such that all page types are associated with each stage. The logical pages are read by applying various types of read operations such as MSB read (e.g. in which a MSB threshold 111 and 115 are used), CSB read (in which two CSB thresholds 112 114 and 116 are used) and LSB read (in which four LSB thresholds 113 and 117 are used).
FIG. 2 shows similar distributions for the case of 2 bpc devices. Four lobes 201, 202, 203 and 204 as well as MSB threshold 212 and two LSB thresholds 211 and 312.
As mentioned, the lobe distributions are not constant throughout the life of the flash and change under various stress conditions. With retention, the distribution become larger and shift towards the erase level. The higher the distribution the larger the shift. This effectively shrinks the effective working window. Both the shrinkage of the window and the fattening of the distributions contribute to the increase in number of errors after performing a page read. FIG. 3 illustrates these effects. Spaced apart lobes 301 overlap and widen due to retention to provide threshold voltage distribution 302.
These effects become significantly worse as the block P/E cycles increase and as the NAND Flash memory technology node shrink.
These stress factors (Node shrink, number of layers in 3D NAND, endurance retention, read disturb) affect reliability due to errors incurred by overlap of lobes. To overcome these issues more advanced memory controllers use advanced ECC and DSP algorithms to overcome the errors incurred by these errors.
FIG. 4 shows a typical prior art NAND flash string and the reading circuitry associated with it. A string is duplicated many times (say 147456 times) in a block and contains several (say 86) Flash memory cells.
Each of the flash memory cells 420 of a string is associated with a different wordline which connects all of the corresponding flash memory cells in the other strings of the block. When a block is chosen, each string is connected to a corresponding bitline by turning on the Bit Line Select and the Ground Select transistors. When a read operation is performed, a sense amplifier 440 is connected to the bit-line and after allowing some time (say 40 uS) for the bit-line voltage to settle, the result is stored by a latch 450. Latch 450 is activated by latch enable (LE) signal. FIG. 4 illustrates a string of thirty two flash memory cells, positioned between a bit line select transistor (for selecting the string) and a ground select transistor (for grounding the string).
In order to measure the charge in a certain cell within a string, all other cells are switched on by applying a high voltage on their gates (given by Vbias) and a comparison voltage, Vth, is applied to the gate of the selected cell. In FIG. 4 the third flash memory cell 420(3) is selected and wordline3 is provided with Vth. Other flash memory cells (1, 2 and 4-32) are fed with Vbias.
If the cell is charged and Vth is not high enough, the gate will not allow current to flow and the sense-amplifier will output a “0”. On the other hand, if the cell is not charge or Vth is high enough, current will flow and the sense-amplifier will output a “1”. Different schemes may exist where the cell being samples is biased with a constant voltage (say Vcc) but in the sense-simplifier a comparison against a reference string is performed which reference value may be determined by some external voltage, Vth.
The bit line and each flash memory cells have certain impedance and capacitance that need to be charged in order to converge to a desired voltage level. This is illustrated in FIG. 5. Curve 510 illustrate the charging of the capacitance of the bit line and/or the selected flash memory cell once the threshold voltage converges and stabilizes to a first target value 520 a single sampling is performed by the latch 450.
The above sampling technique holds when a bit may be obtained only through a single threshold comparison. When more than a single threshold comparison is required, the above procedure may be performed for each threshold and the results may then be combined.